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  • [00:00:31] * Topic is 'http://beagleboard.org/chat has a guide on how to ask questions and links to the logs | never ask to ask, just ask | be patient | pastebin a boot log | http://ahsoftware.de/Beaglebone_Black_Boot_explained.svg | http://beagleboard.org/latest-images | http://beagleboard.org/Support/bone101 | direct bonescript/node.js questions to #beagle-bonescript | books: http://bit.ly/bbb-books'
  • [00:00:31] * Set by KotH!~attila@erica.kinali.ch on Wed Jul 15 13:55:07 UTC 2015
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  • [00:18:29] <vagrantc> hm.
  • [00:18:30] <vagrantc> [ 3.706326] WARNING: CPU: 0 PID: 209 at ../../../drivers/bus/omap_l3_noc.c:147 l3_interrupt_handler+0x27c/0x39c()
  • [00:18:33] <vagrantc> [ 3.706332] 44000000.ocp:L3 Standard Error: MASTER MPU TARGET DSS (Read Link): At Address: 0x00040028 : Data Access in User mode during Functional access
  • [00:18:38] <vagrantc> what's the omap_l3_noc ?
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  • [00:29:04] <sandaldude> Hi folks
  • [00:29:46] <sandaldude> This is actually not strictly a BBB question, but since you're prolly all SBC aficianados...
  • [00:30:14] <sandaldude> Anyone know where on earth I can get hold of a Roseapple Pi to ship to US/Europe?
  • [00:31:05] <sandaldude> All the asian sites are either in Chinese/Singaporean etc and none seem to ship, but guys on YT have somehow gotten hold of them...I'm well stumped
  • [00:32:09] <sandaldude> ?
  • [00:34:01] <sandaldude> Wrong type of question? What do peeps normally ask in here? Resistance differentials across GPIO pins and stuff?
  • [00:34:44] <sandaldude> Anyone connected up any old chips to the BBB? I got a couple of capes to rig up some 68K stuff, but that looks a pretty hefty undertaking...
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  • [00:36:34] <sandaldude> Well anyways nice talking to you... 8[
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  • [02:27:48] <GenTooMan> 8 minutes of waiting...
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  • [03:13:15] <zmatt> uhuh
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  • [03:24:20] <veremit> only 8 minutes, eh?
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  • [04:28:06] <yates> where is register that determines the location of interrupt vector table? i've looked in several manuals and don't see it.
  • [04:28:13] <yates> for the am335x, that is.
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  • [04:31:11] <yates> zmatt: ?
  • [04:32:21] <yates> also where is the definition of the interrupt vector table?
  • [04:33:41] <yates> your vectors.S has init, exc_undef, exc_syscall, etc., located at "vectors" (every four words), but this doesn't match the interrupts defined in Table 6-1 of the am335x trm.
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  • [04:42:09] <abhi_> hello all.. How to add QT to statrtup . I am using debian on bbb. It would be great is someone could help.
  • [04:43:21] <yates> abhi_: what do you mean by "add QT to startup"?
  • [04:43:32] <yates> what do you really want to do?
  • [04:44:26] <abhi_> hi yates. i have a qt gui application. I want that at startup . I have disabled the desktop.
  • [04:45:16] <yates> do you know about systemd?
  • [04:45:31] <abhi_> no i dont
  • [04:45:46] <abhi_> i tries adding to /etc/init.d
  • [04:46:03] <abhi_> but its not getting started
  • [04:46:04] <yates> it basically is what manages what things get started
  • [04:46:13] <yates> yeah, that's not a good approach
  • [04:46:18] <abhi_> oh is it
  • [04:46:29] <yates> hang on - i'll give you an example
  • [04:46:30] <ds2> check the ARM TRM not the AM335 TRM
  • [04:46:40] <abhi_> ya
  • [04:46:42] <ds2> interrupt table should be a Cortex thing
  • [04:46:54] <ds2> cuz you have been shafted by systemd
  • [04:47:03] <ds2> you need to do the systemd config file crap
  • [04:49:43] <yates> abhi_: you need to create a .service file for the application, like this: http://ur1.ca/odw90 -> http://paste.fedoraproject.org/307664/52055741
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  • [04:50:17] <abhi_> i will check
  • [04:50:20] <abhi_> thanks yates
  • [04:50:23] <abhi_> :)
  • [04:50:41] <yates> check the manpages for systemd to find out where to put it.
  • [04:51:22] <abhi_> ya sure i will check
  • [04:51:23] <yates> when you get it created and in the right place, then you enable it to run at startup by issuing the command "systemctl enable xyz.service" (where xyz is the name of your service file)
  • [04:51:45] <yates> ds2: ok, i'll check there - thanks
  • [04:55:08] <yates> well, it's not there either. a search for "dabort" fails
  • [04:55:12] <yates> exc_dabort
  • [04:55:45] <zmatt> yates: btw, I replied to some of your questions earlier, you can find it in the irclog
  • [04:56:14] <zmatt> I wonder if there's a less obnoxious interface to those than http://www.beagleboard.org/irclogs/ ...
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  • [04:56:42] <zmatt> and on a cortex-a8 you can put the vector table at any 32-byte aligned address
  • [04:57:07] <yates> yeah, do you remember what day you responded?
  • [04:58:14] <zmatt> 2016-01-05 around 12:12 (in whatever timezone the irclogs are in)
  • [04:58:44] <veremit> ir-clogs :)
  • [04:59:39] <yates> ok, got it - reading.
  • [04:59:43] <yates> thanks for all that.
  • [05:00:16] <yates> zmatt: re: vector table: yeah sure, but WHAT REGISTER controls that? or did you answer in the log?
  • [05:00:45] <yates> i've looked through the INTC registers and don't see it
  • [05:00:52] <yates> i may be blind.
  • [05:00:53] <zmatt> no since you didn't ask that back then, since it's some cp15 register
  • [05:01:11] <zmatt> easy to find since I set it in my tiny tiny initialization routine in my bbb example
  • [05:01:36] <ds2> you need a mrc/mcr instruction to screw with them
  • [05:01:57] <yates> ok, lemme check that.
  • [05:02:01] <zmatt> https://github.com/mvduin/bbb-asm-demo/blob/master/init.S#L28
  • [05:02:40] <yates> by the way, i found the u-boot code that initializes ddr3. got it ported. testing it now.
  • [05:02:57] <yates> my one day is gone...
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  • [05:03:08] <ds2> the ddr3 init in u-boot should be obvious :D
  • [05:04:16] <zmatt> lol
  • [05:04:35] <yates> it is fairly obvious, ONCE YOU FIND THE RIGHT U-BOOT.
  • [05:04:44] <ds2> hmm?
  • [05:04:56] <yates> it is fairly obvious, ONCE YOU FIND THE RIGHT U-BOOT.
  • [05:05:00] <ds2> you mean you still have u-boot 1's lying around?
  • [05:05:11] * ayjay (~ajp@216.106.134.175) Quit (Ping timeout: 265 seconds)
  • [05:05:27] <yates> i mean without some guidance, there are a bazillion versions of u-boot out there.
  • [05:05:44] <zmatt> I don't think it's particularly obvious in any u-boot... the init code is scattered across many sources and headers
  • [05:05:51] <ds2> they are all very similar, esp. wrt to the foundation init stuff
  • [05:06:06] <ds2> it was to me
  • [05:06:21] <ds2> forgot if it was a quick grep or git log
  • [05:07:06] <yates> i did a bit of grepping, but it wasn't a big problem. it is a little tedious, though
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  • [05:10:07] <zmatt> iirc the values programmed by u-boot contained some oddities though
  • [05:10:20] <zmatt> I'm not really convinced they are optimal
  • [05:11:16] <zmatt> (I forgot the details, though I'm sure I'll run into them again once I find time to finish my own emif init code)
  • [05:15:13] <yates> one thing that is a big question mark is this. i'm not sure if the first subroutine in the top-level routine config_ddr, ddr_pll_config is necessary, due to the statements in section 26.1.4.3 of the am335x trm that ddr dpll is locked to 400 Mhz (as well as other plls necessary)
  • [05:15:44] <zmatt> easy enough to check whether the ddr pll is indeed locked by ROM
  • [05:15:46] <yates> it's not a trivial routine, so i'm hoping it isn't required.
  • [05:16:01] <zmatt> hmm, it should be a trivial routine I think
  • [05:16:12] <yates> no, it isn't.
  • [05:16:41] <yates> iirc, it initializes everything, and there are deep dependencies into the other parts of the board initialization
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  • [05:17:03] <yates> everything meaning the various processor clocks and what not. from basic parameters.
  • [05:17:22] <zmatt> how pointless when public ROM already sets up fairly sane defaults
  • [05:17:32] <zmatt> and linux will overwrite them yet again
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  • [05:18:23] <yates> i have to do some more digging. and reading. and scratching my head.
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  • [05:19:12] <yates> btw, why did you even bother with thumb2 mode? i mean, we've got, what, about 200 words of assembly?
  • [05:19:47] <yates> i.e., code density is not an issue here. right?
  • [05:19:56] <zmatt> why wouldn't I? I mean, with unified assembler syntax there's no difference in source code, and the result is more compact
  • [05:20:04] <zmatt> there's no reason *not* to use thumb2
  • [05:20:20] <zmatt> you can actually assemble the whole thing in arm-mode too if you'd want to for some reason
  • [05:20:28] <yates> of course.
  • [05:21:17] <zmatt> all my baremetal code is thumb2, except for the single instruction at the entrypoint to switch to thumb mode (since pubrom executes the image in arm mode)
  • [05:22:00] <zmatt> I noticed I dump the ddr pll also in my clock-config dump, I'll compile it and run it for you
  • [05:23:54] <yates> zmatt: btw, my question yesterday on the bus error was when i disassembled. there was no writing being done.
  • [05:24:52] <yates> i think i may have had a combination of problems, though, mostly transient. seems like after i reset power, replugged the xds usb, etc., it works fine.
  • [05:24:57] <zmatt> ok
  • [05:27:31] <zmatt> ddr pll is not initialized
  • [05:28:37] <zmatt> http://pastebin.com/HJRK0usu
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  • [05:31:43] <yates> bummer
  • [05:31:51] <zmatt> easy enough to initialize it though
  • [05:31:56] <ds2> i am pretty sure they are not optimal
  • [05:32:54] <yates> few things seem to be easy on this monster of a processor..
  • [05:33:15] <ds2> it isn't that bad
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  • [05:33:37] <ds2> it is your fault for not using U-boot ;)
  • [05:33:42] <yates> neither are finite fields.
  • [05:33:54] <zmatt> finite fields are very elegant
  • [05:34:05] <zmatt> this cpu's prcm isn't remotely
  • [05:34:19] <yates> iirc, galois' five theorems were pretty intense.
  • [05:34:53] <yates> oh, well sure, if your IQ is 165, it's pretty easy...
  • [05:35:32] <zmatt> I do recall having trouble grasping inseparable extensions, though in retrospect i don't understand anymore why I had trouble with them
  • [05:35:42] <zmatt> but that's not an issue with finite fields anyway :)
  • [05:35:56] <yates> that's general field theory, right?
  • [05:36:31] <zmatt> yeah, both finite fields and fields of char 0 only have separable extensions
  • [05:36:59] <yates> don't make me break out my Herstein...
  • [05:38:28] <zmatt> the simplest example of an inseparable one is by taking the function field F_p(X) for some prime p, and then extend it by adjoint the p'th root of X
  • [05:38:36] <zmatt> *adjoin
  • [05:39:30] <yates> zmatt: it's been 12 years since i had this class...
  • [05:39:33] <zmatt> hehe
  • [05:39:39] <zmatt> been a while for me too
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  • [05:40:54] <zmatt> anyhow, the icky part is that the characteristic polynomial has multiple roots... in fact all p of them are the same
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  • [05:41:03] <zmatt> which is a really odd situation
  • [05:41:44] <zmatt> f(x) = x^p - X is irreducible in F_p(X)
  • [05:42:17] <zmatt> yet once you adjoin one root, say α, then it splits as (x - α)^p
  • [05:43:24] <zmatt> I think we drifted slightly off-topic though
  • [05:43:25] <zmatt> ;)
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  • [05:43:47] <yates> yeah.
  • [05:44:20] <yates> if you have the jtag plugged in to the target board, but have disconnected the usb, will it keep the processor halted?
  • [05:44:23] <zmatt> configuring the PLL, I think you just need to write 3 registers
  • [05:44:55] <yates> if i cycle power on the board, will it just stop (i guess at 0x00020000, public rom, as you said)?
  • [05:45:13] <zmatt> depends on whether you enabled break at reset
  • [05:45:16] <yates> that's not bad
  • [05:45:30] <zmatt> and not sure whether it's retained if you unplug, I think it is
  • [05:45:51] <zmatt> it probably does perform a TAP reset if you have a pulldown on nTRST
  • [05:45:53] * Apocx (~quassel@65.246.43.225) Quit (Ping timeout: 246 seconds)
  • [05:46:06] <zmatt> since the xds100v2 will go high-Z on all pins
  • [05:46:46] <zmatt> this might or might not deassert DBGEN, I'm really not sure
  • [05:47:21] <zmatt> generally best to resume the cpu before disconnecting, or power cycle the board
  • [05:47:23] <yates> what initial user-code address does the public rom code jump to after loading it into ram?
  • [05:47:57] <zmatt> in case of MLO (sd/mmc, spi flash, etc) you can specify the address, although it needs to be in internal SRAM
  • [05:48:22] <zmatt> in case of peripheral boot (usb, uart, ethernet) it's always 0x4002f400
  • [05:49:05] <yates> ok.
  • [05:49:41] <zmatt> to change it I think you need to modify it in two places in my demo: the linker script and the makefile (which passes it as argument to the script that builds the mlo header)
  • [05:49:54] <yates> no, it's fine.
  • [05:50:31] <zmatt> sorry I meant 0x402f0400 btw
  • [05:50:52] <zmatt> there's some benefit to using 0x40300000 instead (ocmc ram)
  • [05:50:55] <yates> ok, about these interrupt vectors, e.g., .fun vectors with init, exc_undef, etc., where is this documented
  • [05:50:56] <yates> ?
  • [05:51:08] <yates> what?
  • [05:51:18] <zmatt> since it's accessible from DAP, while the a8-local RAM is only accessible from the a8
  • [05:51:29] <yates> DAP?
  • [05:51:30] <zmatt> so you cannot examine the a8-local RAM without halting the CPU
  • [05:51:46] <zmatt> the Debug Access Port
  • [05:52:01] <zmatt> it has direct access to the L3 interconnect, and to the debug interconnect (L4EMU)
  • [05:52:22] <yates> i'll keep that in mind.
  • [05:52:27] <zmatt> via the debug interconnect it can halt the cpu, examine its state, and make it execute instruction e.g. to access its local RAM and peripherals
  • [05:52:56] <zmatt> I'm not sure if CCS is smart enough to automatically route transactions via DAP when possible
  • [05:53:17] <zmatt> via its L3 access port I mean
  • [05:53:32] <yates> i am really interested in the interrupts. as i stated earlier, all i see is the emuint, commtx, commrx, etc. in table 6-1 of the am335x trm.
  • [05:53:47] <zmatt> that's all outside the cortex-a8
  • [05:53:52] <zmatt> and routed to its IRQ pin
  • [05:54:09] <zmatt> the interrupt controller is not from ARM but from TI
  • [05:54:28] <zmatt> the exception vector table however *is* an ARM-specific thing
  • [05:54:42] <zmatt> hence you find its details in ARM documentation
  • [05:55:10] <zmatt> either the TRM or the architecture reference manual.. I think the former summarizes it and the latter describes it in more detail
  • [05:55:33] <yates> oh, so the interrupt table captioned "ARM Cortex-A8 Interrupts" are not the ARM Cortex-A8 Interrupts?
  • [05:55:39] <zmatt> they are
  • [05:55:40] <yates> sheesh, how stupid of me..
  • [05:55:48] <zmatt> but "interrupt" is only one of the exceptions
  • [05:55:54] <zmatt> the exc_irq
  • [05:56:18] <yates> you just stated they are "outside the cortex-a8". which is it?
  • [05:56:18] <zmatt> a memory fault or undefined instruction isn't an irq
  • [05:57:08] <yates> by irq you mean from a hardware pin?
  • [05:57:21] <zmatt> the interrupt controller is just a separate block meant to filter and prioritize the 128 irqs going to the cortex-a8 subsystem into a single irq signal to the cortex-a8 cpu itself
  • [05:58:25] <yates> i think i see.
  • [05:58:38] <zmatt> this triggers exc_irq
  • [05:58:49] <yates> so the actual cortex a8 interrupts are in which arm document? the trm? the arm?
  • [05:58:58] <zmatt> which then queries the interrupt controller to ask which of the 128 sources has been triggered
  • [05:58:58] <yates> or "exceptions"?
  • [05:59:48] <yates> i see references to EXC_DABORT in the PMU of the arm.
  • [05:59:56] <yates> e.g.,
  • [06:00:13] <zmatt> there are only 8: { reset, undef, syscall, iabort, dabort, <reserved>, irq, fiq }
  • [06:00:32] <zmatt> each is expected to be a 4-byte instruction
  • [06:00:39] <yates> where is that defined? i've looked, sorry if am asking you to hold my hand...
  • [06:00:46] <zmatt> arm architecture ref
  • [06:00:53] <yates> ok
  • [06:01:06] <zmatt> in this case we don't control the actual reset vector
  • [06:01:24] <zmatt> but I use it as entrypoint of my program
  • [06:02:00] <zmatt> it calls init with 'bl' to put the exception table address + 4 into LR, with bit 0 indicating thumb-mode
  • [06:02:01] <yates> i'm looking at the "ARM Architecture Reference Manual: ARMv7-A and ARMv7-R edition" - do i have the wrong document?
  • [06:02:06] <zmatt> nope, it's in there
  • [06:02:19] <yates> a search fo undef fails
  • [06:02:30] <yates> wait, no.
  • [06:02:37] <zmatt> I may have given some of them saner names
  • [06:02:43] <zmatt> i.e. iabort is called "prefetch abort"
  • [06:02:56] <zmatt> undef is still undef though
  • [06:02:59] <zmatt> or "undefined"
  • [06:03:14] <zmatt> triggered by undefined instructions or bogus processor state
  • [06:05:14] <zmatt> btw, the ".handler" and "hret" macros I defined take care of annoying boilerplate and make exceptions behave more sanely, similar to the cortex-M (and I think AArch64 went the same direction as well)
  • [06:05:59] <zmatt> except you still need to push/pop some regs that would be automatically pushed on the cortex-M
  • [06:06:08] <yates> yeah, i finally noticed those.
  • [06:06:28] <yates> pretty tricky to call the one "ret" though! i thought that was an instruction
  • [06:06:53] <zmatt> well, it is an instruction, I just gave it a shorter name
  • [06:07:07] <yates> also, i noticed that's only for a one-level call stack.
  • [06:07:13] <zmatt> no
  • [06:07:21] <zmatt> unified stack, not one-level
  • [06:07:25] <zmatt> it nests just fine
  • [06:07:31] <yates> where are you using a stack?
  • [06:07:41] <yates> you just stuff the return addressing into lr, right?
  • [06:07:52] <yates> ..address
  • [06:08:33] <zmatt> srsfd pushes the lr and spsr of the current cpu mode onto the stack of another cpu mode
  • [06:09:16] <zmatt> oh, that comment on line 12 is wrong, should be "{ lr, spsr } of cur mode" or something
  • [06:09:59] <yates> are you talking about in asm-defs.h?
  • [06:10:03] <zmatt> srs and rfe were introduced exactly to allow using a single stack for all exceptions
  • [06:10:06] <zmatt> no, vectors.S
  • [06:10:22] <zmatt> in the .handler macro definition
  • [06:10:50] <yates> i'm talking about .fun's and ret's.
  • [06:11:03] <zmatt> .fun is just assembler boilerplate
  • [06:12:03] <zmatt> to make the right kind of symbol, and help give them correct sizes
  • [06:12:49] <zmatt> .fun and .var should officially be terminated by .done to set their size, but this is only needed at end of file since each already performs an implicit .done
  • [06:14:19] <zmatt> yates: ARM exceptions are burdened by lots of historical baggage
  • [06:14:45] <zmatt> they're quite possibly the ugliest part of the architecture
  • [06:17:25] <zmatt> hmm, I notice I made changes to this code in my main codebase... maybe I should port those over
  • [06:25:03] <abhi_> hi yates
  • [06:25:09] <zmatt> so, this is what my current start.S looks like, which is the only assembly source file in my C/C++ code: http://gerbil.xs4all.nl/start.S.html
  • [06:25:23] <abhi_> thaks its done . adding qt application to startup
  • [06:28:20] <yates> abhi_: you are welcome. good deal!
  • [06:28:36] <abhi_> but i have one more problem
  • [06:29:07] <abhi_> the thing is that when i boot up it echos some stuffs
  • [06:30:00] <abhi_> means the system
  • [06:30:10] <abhi_> then my qt applications runs
  • [06:30:13] <zmatt> yates: I notice some subtle differences, i.e. in my handler entry I now use "cpsid ia" instead of "cps", this prevents different handlers from interrupting each other as much as possible, saves some headache
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  • [06:34:19] <yates> abhi_: so what?
  • [06:35:09] <yates> zmatt: i was just interested in interrupts from the macro level. all i'm really handling is the switch...
  • [06:35:45] <yates> modify your qt app so it doesn't echo anything, if that's a problem.
  • [06:36:33] <zmatt> yates: so the flow of an interrupt is: irq line asserted to subsystem, if enabled in interrupt controller this triggers the prioritization process and in parallel asserts the nIRQ input of the cortex-a8
  • [06:36:55] <zmatt> if interrupts are enabled then the a8 will take the irq exception
  • [06:38:33] <abhi_> yates: the linux echo's on startup. how to disable that?
  • [06:38:34] <zmatt> my macro (.handler in bbb-asm-demo, henter in my current code) will cleanly stack that on top of the "handler" stack and switch to "handler" mode (as asm-defs explains this is "system mode" currently but could be "supervisor mode" instead)
  • [06:38:48] <zmatt> but with irqs disabled at this point
  • [06:40:05] <zmatt> then the interrupt controller is consulted to figure out what irq was asserted... this is done directly in exc_irq in bbb-asm-demo, but I'd normally do that in C/C++
  • [06:41:28] <zmatt> nested irqs are possible if desired, it would require raising the base priority in the interrupt controller and then reenabling interrupts, and on exit disable irqs, restore base priority, eoi, hret
  • [06:42:17] <zmatt> (this would get you nested irqs similar to those on the cortex-M, but with more boilerplate)
  • [06:45:34] <zmatt> in my current codebase I actually went the other way: I don't enable irqs at all, instead I enter 'idle' after initialization, which does a wfi (which still performs its job with irqs disabled) and directly calls the irq dispatcher
  • [06:45:53] <zmatt> saves overhead of stacking/unstacking the irq exception
  • [06:47:04] <zmatt> basically acts like a main event loop
  • [06:49:28] <abhi_> Hi all . How to disable linux echo on startup. I have qt application and at boot i have added it to systemd. It runs as the system powers up. But before that bbb echos some stuffs. How to disable it
  • [06:50:01] <abhi_> i want to remove all the text
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  • [07:06:41] <yates> zmatt: so by your pastebin, it's just the pll_ddr that has to be set up and enabled?
  • [07:10:45] <zmatt> yep, and I just verified it's easy indeed: to be sure it's disabled write 4 to CM_CLKMODE_DPLL_DDR and poll CM_IDLEST_DPLL_DDR until bit 8 is set
  • [07:12:07] <zmatt> write (24-1) | 400 << 8 to CM_CLKSEL_DPLL_DDR
  • [07:12:12] <yates> don't you have to also setup prescalers etc?
  • [07:12:15] <zmatt> (assuming 24 MHz osc)
  • [07:12:55] <zmatt> write 1 to CM_DIV_M2_DPLL_DDR
  • [07:13:15] <zmatt> write 7 to CM_CLKMODE_DPLL_DDR and poll CM_IDLEST_DPLL_DDR until bit 0 is set
  • [07:13:25] <zmatt> your pll is now locked
  • [07:14:23] <zmatt> (dco at 800 MHz, out-m2 at 400 MHz)
  • [07:15:00] <yates> huh? are you saying the actual output to the ddr memory is 800 MHz?
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  • [07:15:12] <yates> what is "dco"?
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  • [07:15:29] <zmatt> dco is the PLL oscillator freq, out-m2 is the postdivider output
  • [07:15:29] <yates> i thought the emif could only generate a max of 400 MHz.
  • [07:15:39] <zmatt> both are implicitly multiplied by two
  • [07:15:55] <zmatt> you need the even postdivider to get a clean symmetrical clock
  • [07:16:09] <zmatt> hence the PLL is locked at 800 MHz and then divided by two
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  • [07:16:38] <yates> so the actual output to the ddr chip is 400 MHz
  • [07:17:22] <zmatt> wait, I think it actually needs 800 MHz output, lemme check the docs
  • [07:17:28] <yates> is there a diagram you're looking at?
  • [07:17:44] <zmatt> Figure 8-14. DDR PLL Structure
  • [07:19:07] <yates> according to the data sheet, the max DDR clock is 400 MHz. which means our ddr memory is only running at 800 MHz, not 1600 Mhz.
  • [07:19:11] <yates> right?
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  • [07:21:21] <zmatt> it's a little vague, I'm not sure whether the ddr phy macros need to be clocked at the DDR clock speed or twice that speed
  • [07:21:43] <zmatt> ok, DDR clock
  • [07:21:49] <zmatt> then the setup I gave above it right
  • [07:21:50] <zmatt> *is
  • [07:22:01] <zmatt> EMIF runs at 200 MHz
  • [07:22:12] <zmatt> the ddr phy macros at 400 MHz
  • [07:22:31] <zmatt> (there's an implicit /2 divider for the EMIF clock()
  • [07:25:35] <zmatt> so N=23, M=400, M2=1
  • [07:26:00] <zmatt> (again assuming 24 MHz osc)
  • [07:28:08] <yates> are you referring to the "N" in Figure 8-8?
  • [07:29:19] <zmatt> yeah
  • [07:29:35] <zmatt> CM_CLKSEL_DPLL_DDR contains N and M
  • [07:29:39] <zmatt> CM_DIV_M2_DPLL_DDR contains M2
  • [07:29:59] <zmatt> anyway, I gotto do other stuff
  • [07:30:07] <yates> ok.
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  • [09:22:16] <Paul_> my BBB O/S 3.8.13-bone30 ubuntu started crashing every few days, so I created a Debian image 4.1.12-ti-r29, but it seems very slow by comparison.
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  • [09:23:56] <Paul_> Any suggestions which O/S image I should install so the board is stable and fast like ubuntu
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  • [09:34:44] <tbr> install latest official images, and see how that fares?
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  • [11:17:11] <abhi_> hi all. I am using beabglebone black with debian Image 2015-03-01. How to disable the text at startup. It shows Debian GNU/Linux 7 beaglebone tty1 ...
  • [11:17:34] <abhi_> default user:password is [debian:temppwd]
  • [11:17:52] <abhi_> How to disable this text from showing on the lcd
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  • [11:20:36] <tbr> abhi_: you can edit the motd and other things, as for every linux system
  • [11:24:11] <Spidler> abhi_: it's in /etc/motd and /etc/issue
  • [11:24:40] <tbr> and issue.net while you're at it
  • [11:24:52] <Spidler> That too.
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  • [12:41:35] <eliasbakken> Hi, has anyone updated u-boot lately?
  • [12:44:25] <eliasbakken> Looks like the MLO and u-boot.img is layed out in the first sectors of the SDcard, is that correct? On BBB that is.
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  • [13:19:46] <av500> eliasbakken: ?
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  • [13:56:36] <yates> zmatt: why not N = 23, M = 800, and M2 = 2?
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  • [14:24:58] <vamshig51> any one there
  • [14:25:30] <tbr> http://www.catb.org/esr/faqs/smart-questions.html
  • [14:25:43] <Spidler> Nope.
  • [14:27:06] <vamshig51> Hi Spidler
  • [14:27:25] <vamshig51> I would like to contribute to beaglebone black kernel
  • [14:27:26] <Spidler> Hello, vamshig
  • [14:27:44] <vamshig51> what is the procedure that I can submit my changes
  • [14:28:53] <tbr> there is no "BBB kernel" as such
  • [14:29:10] <tbr> what are you specifically interested in?
  • [14:31:43] <vamshig51> cureently I am working on am335x soc
  • [14:31:57] <vamshig51> we have a custome board based on this soc
  • [14:32:35] <vamshig51> I download the kernel from git clone git://github.com/beagleboard/kernel.git
  • [14:33:38] <vamshig51> working on 3.8 branch
  • [14:34:11] <vamshig51> Is there any means that I can submit my changes which will be useful for others
  • [14:36:11] <Spidler> I'd suggest contacting Robert Nelson, https://github.com/RobertCNelson/
  • [14:37:36] <tbr> as far as kernel improvements, I'd consider 3.8 a *very* dead end
  • [14:38:59] <tbr> the rcn specific kernel sources for recent builds are here it seems https://github.com/beagleboard/linux
  • [14:39:15] <tbr> notice the previously mentioned repository has been dead for a year
  • [14:40:57] <tbr> and as Spidler pointed out, you should contact RCN if you want to help improve the BBB specific bits in the linux kernel (and make them fit for upstream)
  • [14:41:18] <Spidler> I'm detaching now, have a good evening all
  • [14:41:20] * Spidler waves
  • [14:41:26] <vamshig51> thank you
  • [14:41:29] <vamshig51> bye
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  • [14:55:15] <yann|work> I don't see a DSP mentionned in the datasheet of the AM3x, gst-dsp won't work on the xM board, or did I miss something ? I can't believe all resellers have discontinued the previous version without having at least on-par video decoding in the newer model :)
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  • [14:59:27] <tbr> yes the AM335x doesn't have a DSP. It has PRUs if that helps you.
  • [14:59:52] <tbr> as you mention gst-dsp it's not really dsp but media acceleration, which the AM335x doesn't have either
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  • [15:10:32] <av500> yann|work: the newer model has no video acceleration
  • [15:10:47] <av500> its not the intended use case
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  • [15:23:31] <yates> does the instruction "and r1, 0xfffffff8" do the logical AND of r1 with the constant 0xfffffff8?
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  • [15:27:04] <yann|work> av500: ah, thanks. Disappointing that vendors all claim that the xM superseded the original, then...
  • [15:27:45] <yann|work> BTW, just noticed an X15 on AliExpress, I thought it was not available yet ?
  • [15:28:06] <yann|work> http://www.aliexpress.com/item/999-0006389-BeagleBoard-X15-BeagleBoard-CircuitCo-Development-Board/32532181129.html?spm=2114.01020208.3.27.ORQCQz&ws_ab_test=searchweb201556_3,searchweb201644_3_10001_10002_10005_10006_10003_10004_62,searchweb201560_8,searchweb1451318400_6149
  • [15:28:11] <alexanderhiam> yates: in what flavor of assembly?
  • [15:28:27] <yates> let's say arm
  • [15:28:43] <yates> the am335x
  • [15:28:49] <alexanderhiam> well it totally depends on what assembly you're using...
  • [15:29:23] <av500> yates: erm, the XM superseeded the Classic
  • [15:29:36] <av500> and yes, the XM had video acceleration like the Classic
  • [15:29:44] <av500> the BBW and BBB have not
  • [15:29:47] <alexanderhiam> I think the AND instruction in ARM assembly takes 3 parameters
  • [15:30:17] <alexanderhiam> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/CIHDAFAI.html
  • [15:30:35] <yates> the syntax above assembles without error
  • [15:30:37] <yates> alexanderhiam: /home/time-src/tool/cgtool/armv7l/gcc-linaro-5.1-2015.08-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-gcc -c -mcpu=cortex-a8 -mfloat-abi=soft -Wa,-mthumb -DTARGET_ARMV7L -DPLATFORM_LINUX_X86 -D_GLIBCXX_DEBUG -I/home/time-src/tool/cgtool/armv7l/gcc-linaro-5.1-2015.08-x86_64_arm-linux-gnueabihf/include/ -I/home/time-src/lib/inc/ -I/usr/local/include/ /home/time-src/app/tst-dram/ddr3_init.sx -o
  • [15:30:37] <yates> /tmp/yates/home/time-src/app/tst-dram/armv7llinux_x86/ddr3_init.o
  • [15:31:40] <yates> i believe it's equivalent to "and r1, r1, 0xfffffff8"
  • [15:31:55] <alexanderhiam> yeah, I'd guess so
  • [15:32:12] <yann|work> but do the xM and the Classic have same kind of video acceleration ?
  • [15:32:50] <yates> i read in the architecture referene manual about the various shifts, but for a negated value of 0xfffffff8, i don't see how you could construct a shift for that.
  • [15:33:17] <yann|work> or has the classic acceleration using DSP, and the xM using PRU ?
  • [15:33:27] <yates> unless they have a one's complement shift or somesuch
  • [15:33:38] <av500> yates: no
  • [15:33:43] <av500> yates: classic and XM both have OMAP3
  • [15:33:50] <av500> so DSP and HW accel for video
  • [15:33:56] <yates> av500: why are you talking to me?
  • [15:33:59] <av500> oops
  • [15:34:01] <av500> yann|work: ^^
  • [15:34:14] <av500> yates: BBW and BBB have PRU but it has nothing to do with video
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  • [15:43:32] <yann|work> av500: when you mention "DSP and HW accel", do you mean there is some other hw acceleration than things like gst-dsp ?
  • [15:43:51] <av500> gst-dsp is SW
  • [15:44:00] <av500> its the glue to link gst and the dsp codecs
  • [15:44:11] <av500> the dsp codecs run on the dsp and use the HW units
  • [15:44:34] <yann|work> ok
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  • [15:45:26] <yann|work> and are there other APIs implemented (VA-API, VDPAU, OMX, whatever) ?
  • [15:45:52] <av500> yeah, there was some OMX foo when people were using OMAP3 for android
  • [15:45:59] <av500> best ignored
  • [15:47:02] <yann|work> yes, the OMX world is a bit strange, it seems :)
  • [15:49:42] <yann|work> otoh, on the rPI going through OMX directly was apparently the most efficient way - even gst uses an omx backend for decoding, but then gluing it to a gst glrenderer was quite inefficient...
  • [15:51:04] <av500> yann|work: everything is best consumed throught a few layers of wrappers
  • [15:51:14] <yann|work> is it possible to get the GPU to read the output of the decoding efficiently, when using gst-dsp (or any other stack, btw)
  • [15:51:20] <cebarth> I've seen some brief comments from RCN via a google search, but is the logo'ed BBB as shipped by Circuitco really GPL compliant?
  • [15:51:34] <av500> yann|work: the GPU does not do the decoding
  • [15:51:37] <av500> on omap3
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  • [15:51:53] <tbr> cebarth: the hardware is not GPL licensed AFAIU
  • [15:51:59] <yann|work> av500: I got that
  • [15:52:19] <cebarth> right, but it ships with GPL software, obviously.
  • [15:52:39] * stefanct (ameno@unaffiliated/stefanct) Quit (Ping timeout: 245 seconds)
  • [15:53:34] <yann|work> my question is more about how to move the decoded frames to the screen - are they just decoded to the framebuffer ?
  • [15:54:10] <yann|work> any colorspace conversion occurs in the accelerator blocks ?
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  • [15:55:33] <av500> yann|work: omap3 has HW overlays
  • [15:55:46] <tbr> cebarth: ah, no idea about that. current images are by RCN. so you can look at his stuff. If you _really_ want compliance (and not just the sources), then you need to contact the vendor who sold you the board anyway.
  • [15:55:47] <av500> so you DSP decodes to YUV and the hardware can show that directly
  • [15:56:08] <av500> or you use the GPU to composite it all into RGB, with of course more memory overhead
  • [15:56:14] <yann|work> mostly asking because eg. SDL2 has moved to using OpenGL as default way to render even a 2D surface, and it is apparently really slower on some platforms than just writing to framebuffer - OTOH, if there is a colorspace conversion to do after HW decoding, doing it with a GL shader may be better
  • [15:56:35] <yann|work> av500: ok, that's cool
  • [15:56:36] <av500> yann|work: Omap3 is bandwith starved
  • [15:56:48] <av500> you dont want the GPU to shuffle data around
  • [15:57:12] <av500> best is to use HW overlays, given that your GUI can handle that
  • [15:57:37] <yann|work> yes, I'm all for HW overlays :)
  • [15:58:42] <av500> yann|work: note that all this gst/DSP stuff on XM is quite dated
  • [15:58:53] <av500> not sure there is a good working config around these days
  • [15:58:57] <av500> best do a time travel
  • [16:03:26] <cebarth> tbr: thanks. My main concern is to be compliant when I ship non-logo element14 boards, but I don't think what Circuitco via Arrow (for example) is shipping is sufficient.
  • [16:04:09] <yann|work> I'm still puzzled by not finding the DSP in the AM3x datasheet - but then, it looks like TI has reorganized their website, and many links from beagleboard.org are wrong (the ones for Classic and xM at least)
  • [16:04:34] <yann|work> av500: which time travel do you advise as best ?
  • [16:04:36] <yates> yann|work: there is no dsp on the AM335x
  • [16:04:47] <tbr> cebarth: if you want to be sure, take off and nuke the emmc from orbit. less convenient for the user, but certainly no software compliance necessary.
  • [16:05:13] <cebarth> indeed
  • [16:05:45] <yates> are you talking about the am33xx?
  • [16:06:01] <yates> er, i mean, omap?
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  • [16:19:29] <yann|work> yates: I'm talking about the SoC in the xM, which http://beagleboard.org/beagleboard-xm advertises as AM37x (which I tend to find strange, are there several board revisions/models with different SoCs ?) and not OMAP
  • [16:19:59] <av500> yann|work: thats TI and their naming schemes
  • [16:20:36] <av500> OMAP3530 / DM3730
  • [16:20:45] <av500> and AM3730 too or so
  • [16:21:34] <tbr> same silly-cone has many names
  • [16:21:38] <yann|work> so is that an OMAP3530 on the xM ?
  • [16:22:47] <av500> OMAP3630 I think aka DM3730
  • [16:22:57] <av500> 3530 is classic, XM was one gen newer
  • [16:23:42] <av500> just call it omap3
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  • [16:27:09] <yann|work> ok. So what's the best course nowaday to decode/display h.264 on those, if not through gst-dsp ?
  • [16:28:08] <av500> use a more modern board?
  • [16:28:21] <av500> you can do ~VGA in SW on the main CPU
  • [16:28:30] <av500> you can get some 720p with gst-dsp
  • [16:28:35] <av500> if you get it to work
  • [16:30:11] <yann|work> I'm aiming more at 1080p and possibly 2160p :)
  • [16:30:48] <yann|work> more modern board, like what for example ? The X15 is not out yet, right ?
  • [16:32:06] <av500> no 1080 on XM for sure
  • [16:34:13] <yann|work> ah, too bad...
  • [16:36:20] <yann|work> OK, I'll focus on other foundries than TI then (unless there are other boards I missed ?)
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  • [17:14:39] <rcn-ee> vagrantc, CONFIG_GPIO_PCF857X=y see: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/arch/arm/configs/omap2plus_defconfig?id=3ab74b89c4d50e6d29d3ace2d400a8a3f1e6de3f
  • [17:14:54] <rcn-ee> vagrantc, you guys have: # CONFIG_GPIO_PCF857X is not set
  • [17:17:35] <rcn-ee> (module would probally work too, but you guys need to enable it. ;) )
  • [17:17:36] <yates> zmatt: i've got the ddr pll initialization done. i am able to read/write the first ddr location (0x80000000) but not the second...
  • [17:17:47] <yates> any ideas?
  • [17:18:16] <yates> i get a dabort if i write 0x80000001
  • [17:18:25] <yates> or anyone...
  • [17:18:52] <yates> yann|work: i see. i too have always found the omap designations highly confusing
  • [17:21:46] <nerdboy> dm81xx (8168 in our case) does 1080p fine
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  • [17:22:07] <nerdboy> has 3 video pipelines or whatever
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  • [17:22:15] <nerdboy> *8168
  • [17:22:32] <nerdboy> rcn-ee: guess what?
  • [17:23:04] <rcn-ee> nerdboy, you go the udoo work ing ;)
  • [17:23:09] <nerdboy> "compatible" imx6sx-sd dt blows chunks on neo
  • [17:23:19] <rcn-ee> haha ;)
  • [17:23:41] <rcn-ee> there suppost to be compaible. ;)
  • [17:23:59] <nerdboy> all their new stuff is in 3.14 udoo fork
  • [17:24:21] <yates> they're supposed
  • [17:24:23] <nerdboy> with backported wifi/bt
  • [17:24:29] <yates> :)
  • [17:24:55] <rcn-ee> yeah... well the backported wifi/bt is better then what they had planned.. thank god for the "backport" project..
  • [17:25:11] <rcn-ee> they wanted to do an external "wifi/bt" module build, but i said, no. ;)
  • [17:25:17] * nerdboy would rather see push to 4.x
  • [17:25:53] <rcn-ee> it's all the "imx6sx" stuff.. i don't think it'll be good on mainline till 4.6/4.7..
  • [17:25:55] <nerdboy> everything should be there in theory
  • [17:26:15] <nerdboy> then wtf is SoloX support doing?
  • [17:26:38] <vagrantc> rcn-ee: thanks, will test and update it!
  • [17:26:55] <nerdboy> it's there but it's not there?
  • [17:27:24] <nerdboy> even their funky usb driver has host support in 4.x
  • [17:27:35] <nerdboy> but not in 3.14...
  • [17:27:38] <rcn-ee> vagrantc, i'm just going thru your config (armmp-lpae) with mainline 4.4.0-rc8 trying to get it to boot to mmc (without initrd..)
  • [17:27:39] <vagrantc> rcn-ee: oh, that just has to do with mmc, not esata?
  • [17:27:56] <vagrantc> oh, i never touch the stuff
  • [17:28:04] <vagrantc> initrd forever!
  • [17:28:28] * nerdboy is still confused wtf the problem is...
  • [17:28:48] <rcn-ee> yeah, which as =m should work.. (there's still another config breaking mmc1 for me.. ;) )
  • [17:28:56] <vagrantc> rcn-ee: although with 4.4.0-rc6 i was able to do rootfs on both microSD and eMMC ...
  • [17:30:37] <rcn-ee> vagrantc, doh! that's why it doesn't help: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/dra7-evm.dts?id=refs/tags/v4.4-rc8#n541
  • [17:30:49] <rcn-ee> it's just for "dra7-evm"...
  • [17:31:12] <rcn-ee> but that should fix hdmi/mmc on dra7-evm if they boot debian's kernel..
  • [17:32:28] <vagrantc> rcn-ee: ah, sounds like a separate bug report i can't verify myself :)
  • [17:32:57] <rcn-ee> i can't verify it either.. (no dra7-evm here)
  • [17:34:35] <vagrantc> well, that's at least one kernel compile test i can avoid
  • [17:34:46] <vagrantc> esata issues still plagues me.
  • [17:35:15] <vagrantc> rcn-ee: could you test eSATA with the debian kernel?
  • [17:35:47] <vagrantc> i've tried 3 different drives, all with the same cable ... but as i recall, it works fine with your 4.1.x kernel
  • [17:36:06] <vagrantc> probably should retest that to be sure
  • [17:36:17] <rcn-ee> a quick grep, dm8168-evm, sh73a0-kzm9q, and sun5i-r8-chip also need CONFIG_GPIO_PCF857X, the "chip" might be a good reason to enable it. ;)
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  • [17:39:27] <rcn-ee> vagrantc, eSATA, yeah that's what i'm trying right now (mmc is in the way). ;)
  • [17:41:06] <vagrantc> rcn-ee: are any of those other boards enabled in the debian kernel config?
  • [17:42:13] <vagrantc> rcn-ee: oh, i'll be getting some of the sun5i-r8-chip boards soonish ... so i'll have the excuse to test then!
  • [17:43:23] <rcn-ee> yeah that's the $9 chip, i'm looking at the other side, a83t's. ;)
  • [17:48:56] * vagrantc is looking all around
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  • [18:00:13] <rcn-ee> vagrantc, darn CONFIG_REGULATOR_PBIAS was in the way... So now it boots and i get the same: ata1: softreset failed (1st FIS failed)
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  • [18:06:10] <vagrantc> rcn-ee: how was it in the way?
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  • [18:06:56] <rcn-ee> about like so: https://paste.debian.net/361410/
  • [18:07:29] <vagrantc> that looks rather familiar
  • [18:08:08] <rcn-ee> i'm tying to move pipp3 to built-in to see what happens..
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  • [21:20:34] <eliasbakken> Ok, so this is a long shot I guess, but I'm getting a "data abort" when trying to use sspi on SPI 1 from u-boot, but not on SPI 0. Could it be that the SPI1 peripheral has been claimed by SPI flash? I see that abort happens during reset and writing the sysconfig register.
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  • [21:28:50] <eliasbakken> Never mind, it was me forgetting to enable the clock for spi1.
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  • [23:50:24] <zmatt> eliasbakken: unfortunately u-boot has crappy error reporting, but yes a data abort generally means one of: 1. misaligned access (u-boot specific, normally allowed) 2. unroutable address 3. target is unpowered, unclocked, held in reset, or otherwise disabled
  • [23:50:57] <zmatt> 4. target doesn't support the particular access, e.g. a write to a read-only register (rare, most peripherals just ignore this)
  • [23:51:14] <zmatt> 3 is most common
  • [23:51:41] <zmatt> 5. request denied by target firewall
  • [23:53:00] <zmatt> and I know at least one peripheral which aborts if you write an inappropriate *value* to a register, but it's not present on the am335x
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